Method of forming metal wiring layer of semiconductor device

ABSTRACT

A method of forming a metal wiring layer of a semiconductor device produces metal wiring that is free of defects. The method includes forming an insulating layer pattern defining a recess on a substrate, forming a conformal first barrier metal layer on the insulating layer pattern, and forming a second barrier metal layer on the first barrier metal layer in such a way that the second barrier metal layer will facilitate the growing of metal from the bottom of the recess such that the metal can fill a bottom part of the recess completely and thus, form damascene wiring. An etch stop layer pattern is formed after the damascene wiring is formed so as to fill the portion of the recess which is not occupied by the damascene wiring.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a divisional of application Ser. No. 11/519,844, filed Sep. 13,2006, which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of forming a metal wiringlayer of a semiconductor device.

2. Description of the Related Art

The line widths of wiring patterns of semiconductor devices are beingmade smaller and smaller to increase the degree of integration of thedevices. The wiring patterns are constituted by a series of metalliclines. Conventionally, metal wiring patterns were formed by depositingmetal on an insulting layer and then patterning the resultant metallayer. However, patterning a metal layer to produce a pattern of verynarrow lines is difficult. An example of an alternative method capableof forming a pattern of metal lines having a very small line width is adamascene process.

The damascene process basically entails forming recesses, e.g.,trenches, in an insulating layer and then filling the recesses withmetal such as A1. In general, such a damascene process comprises formingan A1 layer serving as a seed layer in the recesses by chemical vapordeposition (CVD) process, depositing A1 thereon by physical vapordeposition (PVD), and then conducting a high temperature treatment ofthe resultant structure to grow the A1 crystals and thereby form A1wiring in the recesses. The critical dimension (CD), namely the linewidth, of the wiring formed by a damascene process can be 100 nm orless.

However, a pinch off phenomenon may occur when wiring having such aminute line width is formed using a damascene process. Morespecifically, the pinch off phenomenon is one in which an inlet of arecess in the insulating layer is closed by A1 during the CVD process,i.e., before the PVD process is carried out. In this case, a void isformed in the recessed region. Therefore, the resistance of the wiringis relatively high. Accordingly, the semiconductor device may notoperate stably, and the wiring of the semiconductor device may evenexperience a short circuit during use.

In addition, an IMD (InterMetallic Dielectric) layer is formed on anupper portion of the damascene wiring. Then contact or via holes areformed in the IMD layer. The contact or via holes extend to and exposethe damascene wiring so that the wiring may be connected to an uppermetallic layer. Basically, the contact or via holes are formed byetching the IMD layer. However, the A1 wiring may be etched when the IMDlayer is etched because there is almost no etch selectivity between theoxide of the IMD layer and the A1 of the wiring layer. That is, thedamascene wiring may be damaged during the etching of the IMD layer. Inparticular, short circuits are likely to occur in a thin damascenewiring that has been etched during the forming of the contact or viaholes. Accordingly, it is difficult to manufacture a reliablesemiconductor device whose wiring has a minute line width.

SUMMARY OF THE INVENTION

An object of the invention is to provide a method of forming a reliablemetal wiring layer of a semiconductor device.

According to an aspect of the invention, a method of forming a metalwiring layer of a semiconductor device includes forming an insulatinglayer pattern defining a recess on a substrate, forming a conformalfirst barrier metal layer on the insulating layer pattern, and forming asecond barrier metal layer on the first barrier metal layer in such away that the second barrier metal layer will facilitate the growing ofmetal from the bottom of the recess such that the metal can fill abottom part of the recess completely and thereby form damascene wiringof the wiring layer.

According to another aspect of the invention, the second barrier metallayer comprises a nitride layer, and the process of forming the secondbarrier metal layer is terminated at a time when the nitrogen content ofthat portion of the second barrier metal layer extending within therecess is lower than the nitrogen content of that portion of the secondbarrier metal layer which lies over the upper surface of the insulatinglayer pattern.

According to still another aspect of the invention, the process offorming the second metal barrier layer is terminated when the secondbarrier metal layer extends over only a portion of the first barriermetal layer disposed within the recess. Therefore, part of the firstbarrier metal layer is left exposed after the second barrier metal layerhas been formed.

According to still yet another aspect of the invention, the second metalbarrier layer is formed by a PVD process that is terminated at a pointin time at which the thickness of the second barrier metal layer variesand, in particular, decreases at least in part, in the depth-wisedirection of the recess.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the inventionwill become more apparent from the following detailed description of thepreferred embodiments thereof made with reference to the attacheddrawings in which:

FIG. 1 is a flow chart of a first example of a method of forming a metalwiring layer of a semiconductor device according to the invention.

FIGS. 2 to 9 are respective cross-sectional views of a substrate, andtogether illustrate a sequence of manufacture in the first example ofthe method of forming a metal wiring layer of a semiconductor deviceaccording to the invention.

FIG. 10 is a flow chart of another example of the method of forming ametal wiring layer of a semiconductor device according to the invention.

FIGS. 11 to 16 are respective cross-sectional views of a substrate, andtogether illustrate a sequence of manufacture in the second example ofthe method of forming a metal wiring layer of a semiconductor deviceaccording to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A method of forming a metal wiring layer of a semiconductor deviceaccording to the present invention will now be described with referenceto the drawings. Note, like reference numerals denote like elementsthroughout the drawings.

Referring first to FIGS. 1 and 2, an insulating layer pattern 110defining a recess 112 is formed on a semiconductor substrate 100 (S10).To this end, first, an insulating layer is formed on the semiconductorsubstrate 100. For example, the insulating layer may be a silicon oxidelayer, a silicon nitride layer, or a low-K insulating layer. Also, theinsulating layer may consist of a single film of material or may be alamination. Next, the insulating layer is patterned by, for example,photolithographic and etching processes as is conventional, per se. Atthis time, the depth of the recess 112 is greater than the thickness ofthe damascene wiring to be formed. For example, the depth of the recess112 may be about 2500 Å when a metal wiring layer having a thickness of2000 Å is to be formed.

Referring to FIGS. 1 and 3, a first barrier metal layer 120 is formed onthe upper surface of the insulating layer pattern 110, and alongsurfaces of the insulating layer pattern 110 that define the sides andbottom of the recess 112 (S20). The first barrier metal layer 120 may beformed of Ti, TiN, WN, W, Ta, TaN, Ru, Cu or a combination thereof. Inaddition, the first barrier metal layer 120 may be formed using PVD, CVDor ALD (Atomic Layer Deposition). For example, in the case in which thefirst barrier metal layer 120 is a lamination of a Ti film and a TiNfilm, the Ti film may be formed by a CVD process which uses TiCl4 asprocess gas, and the TiN film may be formed by a thermal CVD processwhich uses TiCl4 and NH3 as process gas.

Referring to FIGS. 1 and 4, a second barrier metal layer 130 havingnitrogen as part of its composition, i.e., a nitride layer, is formedover the first barrier metal layer 120. The nitrogen content of thatportion of the second barrier metal layer 130 disposed over the wallsdefining the recess 112 is lower than the nitrogen content of thatportion of the second barrier metal layer 130 disposed over the uppersurface of the insulating layer pattern 110 (S30). The second barriermetal layer 130 may be a TiN layer. The second barrier metal layer 130may also be formed by a PVD process such as a high density magnetronsputtering process using an HCM (Hollow Cathode Magnetron). In thiscase, a wafer is mounted on a support in a PVD chamber, and Ti issputtered onto the wafer from a hollow cathode Ti target. Also, Ar and agas comprising nitrogen, such as N2, are supplied into the PVD chamber.At this time, the temperature in the PVD chamber may be maintained atabout 25 to 400° C., and about 2 to 40 kW power may be applied to thehollow cathode Ti target.

The second barrier metal layer 130 may be formed in a metallic mode ofoperation of the PVD apparatus. That is, the volume of the Ar suppliedinto the PVD chamber is regulated to be greater than that of the N2 asthe second barrier metal layer 130 is being formed. Preferably, thevolume of the Ar supplied into the PVD chamber is four times that of theN2.

The thickness of the portion of the second barrier metal layer 130disposed on the upper surface of the insulating layer pattern 110 isgreater than the thickness of the other portions of the second barriermetal layer 130. That is, the second barrier metal layer 130 is thethickest above the upper surface of the insulating layer pattern 110,and the thickness of the second barrier metal layer 130 decreasestowards the bottom of the recess 112. That is, a second barrier metallayer 130 is formed by a PVD process characterized in that the materialfrom which the second barrier metal layer 130 is formed is deposited ata rate that decreases as the distance from the target increases, wherebythe thickness of the second barrier metal layer 130 varies according tothe depth of the recess 112. The duration of the PVD process iscontrolled such that the second metal barrier layer 130 never becomesfully developed as in the prior art and thus, has the profile describedabove and illustrated in FIG. 4.

Next, referring to FIGS. 1, 5 and 6, damascene wiring 140 is formed soas to fill a portion of the recess 112 (S40). The damascene wiring 140may be formed of A1. The damascene wiring 140 is formed in-situ bytransferring the substrate 100 on which the second barrier metal layer130 has been formed to a CVD chamber while a vacuum pressure ismaintained. In this case, the damascene wiring 140 may be formed by aMOCVD (Metal Organic CVD) process.

In the forming of the damascene wiring 140, process conditions such asthe deposition time, deposition temperature, deposition pressure, andflow rate of carrier gases may be controlled so as to inhibit a reactionof the A1 outside the recess 112. More specifically, the depositiontemperature is kept as low as possible to minimize the rate at which theA1 is deposited outside the recess 112. For example, the depositiontemperature may be set at 100 to 200° C. In addition, the depositionpressure may be set as high as possible so that a large amount of the A1source gas reaches the inside of the recess 112 within as short a timeas possible. The A1 source gas may comprise MPA (MethylPyrrolidineAlane), DMEAA (DiMethylEthylAmine Alane), DMAH (DiMethylAluminuimHydride), TMAA (TriMethylAmine Alane), TMA, or aluminum boron hydridetrimethylamine. Also, the deposition pressure may be set at 0.1 to 50Torr. Furthermore, when Ar is used as the carrier gas, the Ar may besupplied at a flow rate of, for example, about 50 to 5000 sccm, andpreferably at a flow rate of about 100 to 1000 sccm.

In addition, the nitrogen content of the second barrier metal layer 130influences the growth of A1. More specifically, the growth of the A1layer is inhibited at the upper surface of the insulating layer pattern110 where the nitrogen content of the second barrier metal layer 130 ishigh. Meanwhile, the A1 layer grows at a higher rate at the lowerportion of the recess 112 where the second barrier metal layer 130 isrelatively thin and the nitrogen content of the second barrier metallayer 130 is relatively low, because a number of nuclear sites, i.e.,sites that facilitate the forming of the A1 layer, are present at thebottom of the recess 112. That is, the A1 layer grows best at the bottomof the recess 112 where the second barrier metal layer 130 is thinnestand the nitrogen content thereof is lowest. Accordingly, the A1basically grows from the bottom of the recess 112 towards the upperportion thereof. Subsequently, the substrate 100 is subjected to anannealing process, i.e., is heat treated. The heat treatment improvesthe durability of the damascene wiring 140.

Next, referring to FIGS. 1 and 7, an etch stop layer 150 a is formed inthe recess 112 which is partially filled by the damascene wiring 140(S50). At this time, the etch stop layer 150 a may also be formed overthe upper surface of the insulating layer pattern 110. The etch stoplayer 150 a may be formed of materials which offer a lower contactresistance than the damascene wiring 140 alone. For example, the etchstop layer 150 a may be formed of Ti, TiN, WN, W, Ta, TaN, Ru, Cu, CoWPor a combination thereof, and may be formed of materials which improvethe EM (Electro Migration) characteristic by reacting with the A1 of thedamascene wiring 140. The etch stop layer 150 a includes a first etchstop film 152 a and a second etch stop film 154 a. The first etch stopfilm 152 a may be formed of Ti, and the second etch stop film 154 a maybe formed of TiN. The etch stop layer 150 a may be formed by PVD, CVD,or ALD. In addition, the annealing of the substrate 100 may be performedafter the etch stop layer 150 a is formed.

Next, referring to FIGS. 1 and 8, an etch stop layer pattern 150 isformed on the damascene wiring 140 (S60). More specifically, the etchstop layer pattern 150 is formed by removing select portions of thesecond etch stop film 154 a, the first etch stop film 152 a, the secondbarrier metal layer 130, and the first barrier metal layer 120 to exposethe upper surface of the insulating layer pattern 110. In this respect,the portions of the second etch stop film 154 a, the first etch stopfilm 152 a, the second barrier metal layer 130, and the first barriermetal layer 120 located on the upper surface of the insulating layerpattern 110 may be removed by a CMP (Chemical Mechanical Polishing)process or an etch back process to form the etch stop layer pattern 150.

Next, referring to FIGS. 1 and 9, a contact hole 162 is formed over theetch stop layer pattern 150 (S70). To this end, first, an IMD (InterMetallic Dielectric) layer 160 is formed on the on the insulating layerpattern 110 and etch stop layer pattern 150. Then, a photoresist patternserving as an etch mask is formed on the IMD layer 160. Then the IMDlayer 160 is etched. The contact hole 162 serves to allow the damascenewiring 140 to be connected to a metal layer formed on the IMD layer(160).

The damascene wiring 140 inside the recess 112 is not exposed to theetchant used to form the contact hole 162 in the IMD layer 160 becausethe etch stop layer pattern 150 is disposed on the damascene wiring 140during the etching of the IMD layer. Accordingly, the damascene wiring140 is not damaged when the contact hole 162 is formed.

Another example of the method of forming a metal wiring layer of asemiconductor device will be described with reference to FIGS. 10 and16.

This example of the method of forming a metal wiring layer of asemiconductor device differs from the above-described first example inthat the second barrier metal layer is formed in only a portion of therecess 112.

Referring first to FIGS. 10 and 11, steps S10 and S20 are similar tothose of the first embodiment of the invention and thus, a detaileddescription thereof will be omitted. Next, a second barrier metal layeris formed on only a portion of the first barrier metal layer 120 (S32).More specifically, the second barrier metal layer has a first section132 formed on the upper surface of the insulating layer pattern 110, andon a sidewall of the insulating layer pattern 110 that defines the sidesof the recess 112. The portion of the first section 132 disposed alongthe sides of the recess 112 gradually becomes thinner towards the bottomof the recess 112. The second barrier metal layer also has a secondsection 134 formed at the bottom of the recess 112 as spaced from thefirst section 132. The first and second sections 132 and 134 of thesecond barrier metal layer are formed simultaneously by a PVD processsuch as the high density magnetron sputtering process using an HCM. Thatis, the sections 132, 134 of the second barrier metal layer are formedby a PVD process characterized in that the material from which thesecond barrier metal layer is formed is deposited at a rate thatdecreases as the distance from the target increases. In this example,the material is not deposited on a lower portion of the sides of therecess 112. In this example, the duration of the PVD process iscontrolled to be even shorter than that of the example described abovein connection with FIGS. 1-9 such that the second metal barrier layerbecomes even less developed and thus, has the profile illustrated inFIG. 11. That is, unlike the first example, a discontinuity is formed inthe second metal barrier layer and yet, like the first example, thethickness of the second barrier metal layer varies according to thedepth of the recess 112. Also, the ratio of N to Ti of the secondbarrier metal layer is smaller than that of the first barrier metallayer 120.

Next, referring FIGS. 10, 12 and 13, the damascene wiring 140 is formedso as to fill a portion of the recess 112 (S40). At this time, thegrowth of A1 serving as the damascene wiring 140 starts at the lowerportion of the sides of the recess 112 where the first barrier metallayer 120 is exposed. In this respect, A1 of the second barrier metallayer formed by the PVD process grows slower than the A1 of the firstbarrier metal layer 120 formed by the CVD process as the ratio of N toTi of the second barrier metal layer is smaller than that of the firstbarrier metal layer. Therefore, even though sections 132 and 134 of thesecond barrier metal layer are formed on the first barrier metal layer120, the growth of A1 starts first at the discontinuity of the secondbarrier metal layer (between the sections 132 and 134) in the recess112.

Next, referring to FIGS. 10 and 14 to 16, an etch stop layer 150 a isformed on the damascene wiring 140 (S50). Then, the etch stop layer 150a is patterned to form an etch stop layer pattern 150 (S60).Subsequently, a contact hole 162 is formed on the metal wiring layer asaligned with the recess 112 (S70). These steps are carried out in amanner similar to those described above in connection with the firstexample of the method of forming a wiring layer according to theinvention. Thus a detailed description of these steps will be omitted.

In summary as to the method of forming a metal wiring layer of asemiconductor device according to the present invention, A1 is grownfrom the bottom of the recess 112 by a CVD process. Accordingly, theresulting damascene wiring 140 fills only a portion of the recess 112.Also, a layer of A1 is not formed on the upper surface of the insulatinglayer pattern 110. Moreover, the A1 forming the damascene wiring 140fills the lower portion of the recess 112 uniformly so that a void isnot formed in the recess 112. Hence, a reliable metal wiring layer,i.e., a metal wiring layer that is not prone to short circuiting, isformed.

In addition, the etch stop layer pattern 150 prevents the damascenewiring 140 from being damaged when a contact hole is formed on the metalwiring layer. More specifically, the A1 layer is vulnerable becausethere is almost no etch selectivity between the oxide of the IMD layer160 and the A1 of the damascene wiring 140. However, the etch stop layerpattern 150 stops the etching process and thus, the etchant neverreaches the damascene wiring 140.

Still further, the contact resistance between etch stop layer pattern150 and the damascene wiring 140 is small. Thus, the etch stop layerpattern 150 does not degrade the electrical characteristics of thewiring layer. For all of these reasons, the present invention allowsreliable semiconductor devices to be manufactured.

Finally, although the present invention has been described above inconnection with the preferred embodiments thereof, it is to beunderstood that the scope of the invention is not so limited. On thecontrary, various modifications of and changes to the preferredembodiments will be apparent to those of ordinary skill in the art.Thus, changes to and modifications of the preferred embodiments may fallwithin the true spirit and scope of the invention as defined by theappended claims.

1. A method of forming a metal wiring layer of a semiconductor device,the method comprising: forming an insulating layer pattern defining arecess on a substrate; forming a first barrier metal layer which extendsover an upper surface of the insulating layer pattern, over a side wallof the insulating layer pattern that defines the sides of the recess,and along the bottom of the recess; forming a second barrier metal layeron the first barrier metal layer including over that portion of thefirst barrier metal layer that overlies the upper surface of theinsulating layer pattern and over a portion of the first barrier metallayer that extends within the recess, and wherein the forming of thesecond metal barrier layer is terminated when the second barrier metallayer extends over only a portion of the first barrier metal layerdisposed within the recess such that part of the first barrier metallayer is left exposed after the second barrier metal layer has beenformed; filling a portion of the recess with conductive material whilesaid part of the first barrier metal layer is exposed to thereby formdamascene wiring; and forming an etch stop layer pattern in an upperportion of the recess which is not occupied by the damascene wiring. 2.The method of claim 1, wherein said forming of the second barrier metallayer comprises forming a second barrier metal layer having a sectionwithin the recess that becomes thinner in a direction from the uppersurface of the insulating layer towards the bottom of the recess.
 3. Themethod of claim 1, wherein the forming of the second barrier metal layercomprises forming a second barrier metal layer that has a first sectionextending over a sidewall of the insulating layer pattern that definesthe sides of the recess and a second section that extends across thebottom of the recess, and wherein the second barrier metal layer has adiscontinuity between the first and second sections thereof.
 4. Themethod of claim 1, wherein the first barrier metal layer and the secondbarrier metal layer are formed of TiN, respectively.
 5. The method ofclaim 4, wherein the ratio of N to Ti of the second barrier metal layeris smaller than that of the first barrier metal layer.
 6. The method ofclaim 1, wherein the first barrier metal layer is formed by a CVDprocess or an ALD process.
 7. The method of claim 1, wherein the secondbarrier metal layer is formed by a PVD process.
 8. The method of claim6, wherein the second barrier metal layer is formed by a PVD process. 9.The method of claim 1, wherein the forming of the damascene wiringcomprises growing A1 from said part of the first barrier metal layerleft exposed after the second barrier metal layer has been formed. 10.The method of claim 1, wherein the forming of the etch stop layerpattern comprises forming a first etch stop film and subsequentlyforming a second etch stop film on the first etch stop film.
 11. Themethod of claim 10, wherein the forming of the etch stop layer patterncomprises: forming the first etch stop film and the second etch stopfilm to each extend over the upper surface of the insulating layerpattern as well as in the portion of the recess which is not occupiedwith the damascene wiring, and subsequently selectively removingrespective portions of the second etch stop film, the first etch stopfilm, the second barrier metal layer, and the first barrier metal layerto expose the upper surface of the insulating layer pattern.
 12. Themethod of claim 1, further comprising forming a contact hole alignedwith the recess, after the etch stop layer pattern has been formed. 13.A method of forming a metal wiring layer of a semiconductor device, themethod comprising: forming an insulating layer pattern defining a recesson a substrate; forming a first barrier metal layer which extends overan upper surface of the insulating layer pattern, over a side wall ofthe insulating layer pattern that defines the sides of the recess, andalong the bottom of the recess; forming a second barrier metal layer onthe first barrier metal layer including over that portion of the firstbarrier metal layer that overlies the upper surface of the insulatinglayer pattern and over the first barrier metal within the recess, andwherein the forming of the second metal barrier layer comprises a PVDprocess that is terminated at a point in time at which the thickness ofthe second barrier metal layer varies in the depth-wise direction of therecess; filling a portion of the recess with conductive material whilesaid part of the first barrier metal layer is exposed to thereby formdamascene wiring; and forming an etch stop layer pattern in an upperportion of the recess which is not occupied by the damascene wiring. 14.The method of claim 13, wherein the PVD process is a high densitymagnetron sputtering process.